Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors’ knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.Peer Reviewe

An LMS-based adaptive predistorter for cancelling nonlinear memory effects in RF power amplifiers

This paper presents the design of an adaptive Digital Predistorter (DPD) for Power Amplifier (PA) linearization whoseimplementation and real time adaptation can be fully performed in a Field Programmable Gate Array (FPGA). The distinctive characteristic of this adaptive DPD is its straightforward deduction from a Nonlinear Auto Regressive Moving Average (NARMA) PA model and the possibility to be completely implemented in a FPGA without the need of an additional digital signal processor performing the DPD adaptation. The adaptive DPD presents a NARMA structure that can be implemented by means of Look-Up Tables (LUTs). This configuration results in a Multi-LUT implementation where LUT contents are directly updated by means of an LMS algorithm. Details on the internal adaptive DPD organization as well as its linearization capabilities are provided, taking into account memory effects compensation

Implémentation de techniques de linéarisation et d'amélioration du rendement pour les amplificateurs de puissance RF

L'antagonisme entre la capacité d'émission d'informations haut débit (linéarité) et le rendement énergétique, dans le contexte des émetteurs radio, est l'axe des travaux de cette thèse. Nous proposons une architecture matérielle basé sur circuits FPGA1 pour l'implémentation de fonctionnalités de prédistorsion numérique (DPD) pour la linéarisation d'amplificateurs RF. Nous articulons nos approches a partir de la séparation entre les processus de prédistorsion et d'adaptation. Ainsi, nous pouvons proposer une structure matérielle (le BPC2 ou Cellule Basique de Prédistorsion) bien adaptée pour l'implémentation du module de prédistorsion. Le module de prédistorsion basé sur BPC peut être reconfigurable au besoin, et, en plus, il reste indépendant de la méthodologie particulière de dérivation de la fonction de prédistorsion. Afin d'effectuer des validations, deux prototypes permet tant de tester des stratégies de prédistorsion performantes et novatrices ont été mis en oeuvre. Dans un premier temps, nous avons implémenté un système DPD basé sur la théorie des systèmes hyperstables sur une plateforme mixte FPGA/DSP3. En complément des résultats expérimentaux, nous rentrons dans le détail des fonctions complémentaires a la prédistorsion et l'adaptation nécessaires pour produire la prédistorsion. Le deuxième prototype adresse la linéarisation et la compensation des effets mémoire de l'amplificateur RF. Nous présentons et validons expérimentalement une structure de prédistorsion du type NARMA4, implémentée au moyen d'un réseau de cellules BPC. Au passage, nous étudions la consommation de la prédistorsion et son impact sur le rendement. Si l'utilisation de la prédistorsion s'avère inévitable pour contrer les effets mémoire, nous proposons de dégrader la Classe de l'amplificateur, dans le but d'obtenir un émetteur aussi linéaire mais plus performant énergétiquement. Finalement, au del a de la prédistorsion seule, nous proposons, analysons et validons expérimentalement un système de prédistorsion + commande dynamique de l'alimentation de l'amplificateur RF. La structure de traitement du signal numérique développée, permet de : 1/ prédistordre le signal et 2/ commander des modulateurs d'amplitude lents (par rapport à la largeur de bande de l'application cible, mais ayant de forts rendements de conversion). L'inclusion de capacités de pilotage de l'alimentation autour de la prédistorsion s'avère peu côuteuse et permet d'atteindre des rendements améliorés sans perte de linéaritéThe antagonism between information capacity and energetic efficiency in the context of wireless communications, more precisely : the trade-off between transmitter linearity and its efficiency ; is the main driver of this thesis. A FPGA5-based architecture for digital predistortion (DPD) linearizers for RF power amplifiers is proposed in this thesis. By means of separating the adaptation process from the predistortion itself, a convenient, simple hardware building block for the DPD architecture inside the FPGA {the Basic Predistortion Cell (BPC){ has been identified. A BPC-based architecture provides independency from the particular DPD function derivation method, and it is easily scalable and reconfigurable, depending on the operation mode and degree of impairments introduced by the transmitter chain in each particular case. In order to support those claims and provide experimental evidence, two main different prototyping scenarios have been developed. In the first one, a DPD adaptive linearizer based on the passivity theory (hyperstable systems) has been designed and implemented on a low-cost mixed FPGA/DSP platform. Besides experimental results, complementary signal proces sing techniques to DPD are also addressed, thus giving a wide insight on realistic scenarios of DPD systems. In the second scenario, an advanced, adaptive DPD system aimed at compensating not only PA's nonlinear behavior, but also its memory effects, is presented. It is based on a Nonlinear Auto-Regressive Moving Average7 structure which is mapped into hardware using a BPC grid-structure. Besides the experimental results on PA efficiency and linearity, FPGA implementation issues {such as adaptation and power consumption{ are also studied. The manipulation of the PA class of operation to improve its efficiency, provided that DPD may be unavoidable due to the impact of memory effects, is discussed as well. Finally, to further improve efficiency, a DPD linearizer with dynamic supply built-in capabilities has been proposed and implemented as discussed in the last part of this thesis. There, an efficient, bandwidth limited, switched DC-DC converter is in charge of the PA supply modulation. The thorough design procedure targeting a FPGA implementation shows how the necessary functions for commanding the supply modulator can be seamlessly integrated within the DPD processor. The experimental results highlight how the proposed solution maintains linearity and enhances the PA efficiency when compared to a DPD-only methodINIST-CNRS (INIST), under shelf-number: RP 17272 / SudocSudocFranceF

Crinkly curves, Markov partitions and dimension

SIGLEAvailable from British Library Lending Division - LD:D56481/85 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

A recursive digital predistorter for linearizing RF power amplifiers with memory effects

A nonlinear auto-regressive moving average (ARMA) structure capable of compensating nonlinear memory effects in RF power amplifiers is here presented. Results on the linearity improvement, in both in-band and out-of-band distortion compensation, achieved by this baseband digital predistorter are provided. Moreover, a study on this nonlinear ARMA system stability is also reported

A new digital predictive predistorter for behavioral power amplifier linearization

This letter presents a new digital adaptive predistorter (PD) for power amplifier (PA) linearization based on a nonlinear auto-regressive moving average (NARMA) structure. The distinctive characteristic of this PD is its straightforward deduction from the NARMA PA model, without the need of using an indirect learningapproachto identify the PD function.The PD itself presents a NARMA structure, and hence it can be quickly implemented by means of lookup tables. Single and multicarrier modulated signals collected from a three-stage LDMOS class AB PA, with a maximum output power of 48-dBm CW have been used to validate the linearity performance of this new predictive predistorter.Peer Reviewe

Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors’ knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.Peer Reviewe

A new digital predictive predistorter for behavioral power amplifier linearization

This letter presents a new digital adaptive predistorter (PD) for power amplifier (PA) linearization based on a nonlinear auto-regressive moving average (NARMA) structure. The distinctive characteristic of this PD is its straightforward deduction from the NARMA PA model, without the need of using an indirect learningapproachto identify the PD function.The PD itself presents a NARMA structure, and hence it can be quickly implemented by means of lookup tables. Single and multicarrier modulated signals collected from a three-stage LDMOS class AB PA, with a maximum output power of 48-dBm CW have been used to validate the linearity performance of this new predictive predistorter.Peer Reviewe

An LMS-based adaptive predistorter for cancelling nonlinear memory effects in RF power amplifiers

This paper presents the design of an adaptive Digital Predistorter (DPD) for Power Amplifier (PA) linearization whoseimplementation and real time adaptation can be fully performed in a Field Programmable Gate Array (FPGA). The distinctive characteristic of this adaptive DPD is its straightforward deduction from a Nonlinear Auto Regressive Moving Average (NARMA) PA model and the possibility to be completely implemented in a FPGA without the need of an additional digital signal processor performing the DPD adaptation. The adaptive DPD presents a NARMA structure that can be implemented by means of Look-Up Tables (LUTs). This configuration results in a Multi-LUT implementation where LUT contents are directly updated by means of an LMS algorithm. Details on the internal adaptive DPD organization as well as its linearization capabilities are provided, taking into account memory effects compensation

Multi look-up table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors’ knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.Peer Reviewe